The present invention is directed generally to digital apparatus, and more particularly to apparatus for communicating the state transitions of a periodic digital signal from one circuit node to another circuit node with a minimum of delay.
Much of today's digital electronics is implemented in large scale integration (LSI) dominated by a logic family called complementary MOS (CMOS). The basic structure of CMOS logic is the CMOS inverter in which an upper PMOS transistor is connected to a lower NMOS transistor in a type of push-pull configuration. The advantage of this configuration is that little current is conducted when the inverter is in one of its non-switching states: when the input signal is a logic low level (e.g., ground or a negative voltage) the bottom NMOS transistor is off while the top (PMOS) transistor pulls the output toward a supply voltage; when the input receives a logic high level input the transistors reverses their states. In addition to less power consumption than other logic families (e.g., transistor-transistor-logic), CMOS can provide such additional advantages as generating less heat, and requiring less semiconductor space, permitting an integrated circuit to be more densely packed.
However, a severe limitation of MOS circuits is the various capacitances inherent in MOS structures which affects switching speeds and, thereby, speed of operation. Limiting the size of MOS transistors will, in turn, limit the inherent capacitances, but this limits the current provided by the transistors to drive the capacitance of the next stage. There are times when large capacitances (e.g., in the form of a number of MOS logic gates) must be driven by an MOS developed signal, necessitating larger CMOS transistors. In such cases the resultant delay can be minimized by using a series of cascaded CMOS inverters ("buffering up" as it is sometimes called in this art) to convey the driving signal, each inverter being larger in size than the one before it until the last stage is reached with the structure necessary to drive the capacitance with a minimum of delay.
The speed of an MOS transistor is related to its size, i.e., the width and length of the channels of the MOS transistors. It is generally standard practice in this art to fabricate MOS transistors (both PMOS and NMOS transistor structures) with a channel length that is the minimum allowed by the manufacturing technology employed, since this maximizes the current the transistor can provide while minimizing the capacitance of the transistor. Accordingly, discussion of the size of a transistor herein, unless otherwise noted, shall refer to the size of the channel width of the transistor in question.
Returning to the CMOS inverter structure, the speed with which the PMOS and NMOS transistors of a CMOS inverter can respectively pull the output node toward one voltage or another, i.e, the delay of the inverter, is directly related to the size of the driving transistor, and to the size of the transistor(s) that is being driven. This relationship, often termed "fanout," is the ratio of the size (i.e., channel width) of the driven transistor or transistors to that of the driving transistor.
The signals of concern herein are periodic digital pulses having positive and negative-going state transitions. MOS circuits are usually designed to transmit both transitions with substantially equal delay from one circuit node to another. Such designs tend to exhibit a moderately long delay in the transmission of both transitions.
It is believed known to enhance the size of one or the other of the transistors of a CMOS pair so that it is capable of switching faster on one transition of an applied input signal than the other, thereby communicating that one transition with less delay than the other. Thus, a series of such CMOS stages can be formed to pass one transition of a signal with less delay than the other transition, and more specifically, with less delay than that of an inverter designed to transmit both transitions with substantially the same delay. The problem with this approach, however, is that the delayed transition arrives much later than desired.